Field
Aspects of the present disclosure relate to memory circuits, and more particularly to static random-access memory (SRAM) bit cells with write-assist circuits.
Background
As semiconductor technology scales down, an increasing number of transistors can be integrated into a single chip. Fluctuation of the threshold voltage (Vth), however, increases with technology scaling due to random dopant fluctuation (RDF), line edge roughness (LER), and short channel effects (SCE), which affect small-geometry devices to a greater degree because the threshold voltage can affect individual transistors within a cell. As a result, it is more difficult to analyze the results of using one cell on a semiconductor chip as opposed to a different cell on the same chip.
In particular, as static random-access memory (SRAM) is one of the components in a system-on-chip (SoC) and occupies a large portion of the SoC, an SRAM cell is typically designed using very small transistors for a high integration density. Thus, the stability and write ability of the SRAM gradually degrade, and it is very challenging for SRAM to achieve a sufficient yield in smaller technologies, such as 22 nm technology and beyond, with planar bulk metal-oxide-semiconductor field-effect transistors (MOSFETs).
Extremely thin silicon-on-insulator (ETSOI) materials are attractive candidates for 22 nm and beyond technology nodes to resolve the problems of planar bulk MOSFETs. FIG. 1 shows a schematic cross-sectional view of an ETSOI structure with a back-gate.
A transistor 100 is shown with a source 102, gate 104, and a drain 106 that create changing electric fields that control current flow between the source 102 and drain 106 in a channel 107. A buried oxide (BOX) layer 108 electrically isolates the source 102, the gate 104, and the drain 106 until the proper voltages are placed on the source 102, the gate 104, and the drain 106 contacts to create electrical fields under the gate 104. The gate 104 is insulated from the channel 107 by an insulator layer 109 that allows for current flow. A back-gate 110 is controlled by a well contact 112, which is also electrically coupled to a substrate 114; the back-gate 110 can be used to more precisely control the electrical fields between the source 102 and the drain 106 to open the channel 107. Vth is the threshold voltage specified to create the proper electrical fields across the gate 104, which allows current to flow between the source 102 and the drain 106 in the channel 107.
Random dopant fluctuation (RDF) is the major contributor to the Vth variation, and the extremely thin silicon-on-insulator (ETSOI) material reduces the RDF by using an undoped channel underneath the gate 104. Further, the ETSOI material provides a better short channel control than planar bulk MOSFETs due to the thin channel 107 body. In addition, ETSOI devices with a thin BOX layer 108 can control the Vth by changing the back-gate voltage via the well contact 112, which is similar to body bias in planar bulk MOSFETs, where the substrate voltage is controlled. The leakage current (i.e., current that flows between the source 102 and the drain 106 of the planar bulk MOSFETs) however, drastically increases due to the p-n junction leakage current (between the substrate 114 and the source 102/drain 106) when a forward body (substrate 114) bias is applied. Such a forward bias provides enough of an electric field to the channel 107, which allows current between the source 102 and the drain 106, even when the channel 107 is designed to be closed. Such leakage current in the planar bulk MOSFET body bias approach limits the body bias voltage range that is used to control the RDF and other Vth issues.